A family, not one chip
ESP32 is a name Espressif Systems uses for a family of microcontrollers with radios on the same chip. The original part, the chip simply called ESP32, is described in its datasheet as a single 2.4 GHz Wi-Fi-and-Bluetooth combo chip made in a 40 nm low-power process. Espressif’s getting-started guide lists what it integrates: Wi-Fi in the 2.4 GHz band, Bluetooth, dual Xtensa 32-bit LX6 processor cores, an ultra-low-power coprocessor, and a set of peripherals.
Later chips keep the ESP32 name with a series letter. The Rust on ESP Book groups them by processor architecture: the ESP32 and the ESP32-S series use Xtensa cores, and the ESP32-C and ESP32-H series use RISC-V cores. The radios differ as well. Some have Wi-Fi and Bluetooth LE, the ESP32-S2 has no Bluetooth, the ESP32-H2 has no Wi-Fi, and the ESP32-C6 and ESP32-H2 add IEEE 802.15.4 for Zigbee and Thread. Sending data from an ESP32 to a phone has a table of which radio each chip has.
Cores and memory across the family
The processor and on-chip memory also vary. Each row below is from Espressif’s datasheet for that chip:
| Chip | Processor | On-chip SRAM |
|---|---|---|
| ESP32 | One or two Xtensa LX6 cores, up to 240 MHz | 520 KB, plus 16 KB in the RTC domain |
| ESP32-S3 | Dual-core Xtensa LX7, up to 240 MHz | 512 KB, plus 16 KB in the RTC domain |
| ESP32-C3 | Single-core RISC-V, up to 160 MHz | 400 KB, of which 16 KB is cache |
| ESP32-C6 | RISC-V high-power core up to 160 MHz, plus a low-power RISC-V core up to 20 MHz | 512 KB high-power SRAM, plus 16 KB low-power SRAM |
| ESP32-H2 | Single-core RISC-V, up to 96 MHz | 320 KB |
Program storage is separate from that SRAM. The original ESP32 runs code from external QSPI flash through a cache, and its datasheet states that up to 16 MB of external flash can be mapped into the processor’s memory space. Some variants carry the flash inside the chip package instead, which the part number shows.
Chip, module and development board
Products and prototypes do not have to start from the bare chip. A module puts the chip on a small board with its flash and an antenna; Espressif’s ESP32-WROOM-32E, for example, is a Wi-Fi, Bluetooth and Bluetooth LE module with 4, 8 or 16 MB of SPI flash and either a PCB antenna or a connector for an external one. A development board adds USB, buttons and pin headers around a module. The Rust on ESP Book uses the ESP32-C6-DevKitC-1 as its example: an ESP32-C6-WROOM-1 module with 8 MB of SPI flash, a USB-to-UART bridge for flashing and serial communication, a second USB port for USB and JTAG debugging, and Boot and Reset buttons for entering firmware download mode.
So when someone says “an ESP32”, check which chip, which module and how much flash. Those three facts decide what firmware will fit and which radios it can use.
How you program one
Espressif’s own framework is ESP-IDF, which it describes as intended for developing Internet of Things applications with Wi-Fi, Bluetooth, power management and other system features. ESP-IDF includes the FreeRTOS kernel as a component, so all ESP-IDF applications are written on FreeRTOS. Espressif’s version is based on FreeRTOS 10.5.1 with changes to run on two cores at once.
Other routes exist. Espressif maintains an Arduino core for ESP32 built on ESP-IDF, and Zephyr has board support for Espressif boards such as the ESP32-DevKitC.
Rust works in two ways. Code can run on top of ESP-IDF with the standard library, which Rust’s platform support list shows for its ESP-IDF targets, or bare metal in no_std mode using esp-hal, which supports the ESP32 and the ESP32-C, ESP32-H, ESP32-P and ESP32-S series. The RISC-V chips build with the standard Rust toolchain. The Xtensa chips need Espressif’s forks of LLVM and the Rust compiler, since LLVM does not yet support Xtensa and Espressif is working to upstream its changes.
Security features to know about
The original ESP32’s datasheet lists secure boot, flash encryption, one-time-programmable memory, and hardware acceleration for AES, SHA-2, RSA and random number generation. Two of them shape how a product ships:
- Secure boot. With Secure Boot v2, the first-stage bootloader in ROM checks the signature of the second-stage bootloader, which checks the application before it runs. ESP-IDF documents Secure Boot v2 for the ESP32 from chip revision 3.0 onwards.
- Flash encryption. This encrypts the contents of the off-chip flash, so reading the flash chip directly does not recover most of its contents. ESP-IDF warns that enabling it limits later update options, so read the documentation before turning it on.
Both are controlled by eFuses, which Espressif describes as one-time programmable, so plan them before production. When firmware needs keys, use the hardware random number generator, and note that ESP-IDF’s random number documentation lists the conditions under which it produces true random numbers, such as the Wi-Fi or Bluetooth radio being enabled.